【超威半导体2018校园招聘】超威半导体前程无忧官方校园招聘网

校招职位地点主要分布在上海和北京，查看更多职位信息请点击登录网申页面。

ASIC Design Verification Engineer	EE, CS, OR RELATED
• Good understanding on ASIC design verification flow • Programming knowledge on Verilog/SystemVerilog, C/C++ • Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
ASIC Design Verification Engineer	EE, CS, OR RELATED
• Good understanding on ASIC design verification flow • Programming knowledge on Verilog/SystemVerilog, C/C++ • Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
ASIC Front-End Design Engineer	EE, CS, OR RELATED
• Develop RTL code for Block / IP or SoC top level • Working with project lead to define FEINT flow setting, including synthesis, equivalence check flow. Define frequency target, power strategy and etc. • Regular run FEINT flow, check quality, drive/co-work IP team on issue solving and QoR improvement. • Work very closely with physical design engineers to help on floorplan, timing closure, power design validation and etc.
Physical Design Engineer	EE, CS, OR RELATED
• Familiar with general IC design flow, familiar with physical design flow and EDA tool (Synopsys or Cadence) is a plus. • Familiar with Linux, skill in scripts including perl/tcl/cshell/python is a plus. • Good communication skills, proactive and team work.
ASIC Design methodology Engineer	EE, CS, OR RELATED
• Participate in the design and implementation of the leading edge, front-end or back-end ASIC design flow which covers from logical design to physical implementation (synthesis, place and route etc) • Be familiar with Linux working environment • Experience in program with one or more languages (CShell, TCL, Perl or python etc.) is a plus
DFT Design Engineer	EE, CS, OR RELATED
• Implement DFT features including SCAN, Boundary SCAN, MBIST, Analog Macro test logic and etc. • Generate DFT related timing constraints and work with PD team for timing closure. • Participate in ATE bring-up and debug the DFT patterns on ATE.
DFT Design Engineer	EE, CS, OR RELATED
• Implement DFT features including SCAN, Boundary SCAN, MBIST, Analog Macro test logic and etc. • Generate DFT related timing constraints and work with PD team for timing closure. • Participate in ATE bring-up and debug the DFT patterns on ATE.
Senior Software Development Engineer	EE, CS, SW, or RELATED
• Work as part of the global Software Customer Support engineering team to design and maintain the graphics device driver and other software components • Resolve problem reports related to graphics device driver including troubleshooting, debugging, & defect correction • Specify, design, and implement new ASIC and software features
Graphics Driver Enginee	EE, CS, SW, or RELATED
• Design, develop and debug kernel mode driver, ISP driver, graphics driver, including DirectX/OpenGL/Vulkan drivers. • Work on supporting next generation Microsoft Windows, Linux and Virtualization operation system. • Work on bring up and support AMD next generation APU/GPU.
System Software Engineer	EE, CS, SW, or RELATED
• Design, develop, and debug BIOS (System Software) or UEFI Firmware for internal/external systems and platforms that use AMD APU/CPU, AMD chipset, and 3rd party chipsets. • Participant in day-to-day BIOS development work using PC assembly and C languages; will need to interact with internal organizations and customers. • Comfortable working with PC hardware and platform issues.
Systems Design Engineer -Debug Engineer	EE, CS, OR RELATED
• Support new product bring-up and debug • Work with validation and cross functional teams providing support on silicon related issues. • Create test procedures and generate technical documents as needed.
Systems Design Engineer -IPSE Engineer	EE, CS, OR RELATED
• Work closely with IP design team to define IP validation test plan for both pre-silicon (emulation) and post-silicon. • Lead ASIC/ IP feature bring-up and validation, ensure coverage and schedule will meet silicon tape-out date. • Drive cross-team (ASIC design, platform, driver) collaboration to enable IP features and optimize performance.
Graphic Performance Verification and Analysis	EE, CS, OR RELATED
• Co-Work with World Wide Performance Verification and Design Team. • Initiate and Lead Research on GPU architect . • Write performance analysis tools. Familiar with Graphics Algorithm/Graphics Pipeline.
Graphics and parallel computing software architect	EE, CS, OR RELATED
• Co-Work with World Wide Performance analysis and Design Team. • Development experience with device drivers or compiler(graphics, networking). • Any research or develop experience related to GameEngine/ Renderman/ MentalRay/GI renderer.
Machine Deep learning Software Development Engineere	CS,EE,CE, or EQUIVALENT
• Responsible for AMD Machine/Deep Learning Software Development (Driver, SDK, Frameworks); • Develop testing for Machine/Deep Learning products to ensure functionality, compatibility and performance; • Performance/Power Analysis, Optimization, Tuning of Deep Learning Kernels • Triage, isolate failures of root cause analysis and work with global development team to verify fixes;