Position Title: ASIC Engineer (Clock)
The NVIDIA Clocks group is looking for an ASIC engineer with logic design, timing closure, or verification experience. Modern clocking design needs to balance high frequency clocks with function, DFT, circuit and power, physical design constraints.
Responsibilities:
- Micro-architecture and module design for high speed logics
- Perform Synthesis, STA, CDC or formal at module or chip level.
- Chip level integration and flow development
- Methodology development for above tasks.
MINIMUM REQUIREMENTS:
- BS / MS in electrical / computer engineering and related.
- Have ASIC design, synthesis or timing closure experience.
- Strong programming skills in Verilog, Perl/Phython, TCL or C/C++
- Understand DFT or OCC is a plus
- Familiar with standard tools is a plus, like DC/PT, Verdi/DVE, NCSIM/VCS, etc
- Excellent analytical and problem solving skills
- Fluent English (both written and spoken) and excellent communication skills
- Good team work spirit, easy to cooperate with team members